1. Field of the Invention
This invention relates to latching comparator circuits for use in devices such as analog-to-digital converters (ADCs), and more particularly to high speed latching comparator circuits that utilize devices such as tunnel diodes having a region of negative impedance separating high and low voltage regions of positive impedance.
2. Description of the Related Art
Latching comparator circuits are used in applications such as ADCs and flip-flop circuits. However, their switching speed has been limited, which imposes a corresponding limitation upon the speed of the device into which they are incorporated.
The circuit design for a conventional latching comparator such as that used in a parallel ("flash") ADC is shown in FIG. 1. A differentially-connected input transistor pair Q1, Q2 is respectively biased by input and reference voltages. The transistors are connected to a positive voltage bus V.sub.cc through respective load resistors R.sub.L1 and R.sub.L2. While illustrated as npn bipolar devices, the transistors could also be pnp bipolars or field effect transistors. Complementary logic outputs V.sub.o and V.sub.o are taken from the collectors of Q2 and Q1, while a pair of regenerative latching transistors Q3, Q4 latch the logic outputs in the states established by the input pair. The base and collector of Q3 are connected to V.sub.o and V.sub.o respectively, while the base and collector of Q4 are collected to V.sub.o and V.sub.o respectively. Q3 and Q4 have their emitters connected together as a differential pair.
A third differential transistor pair Q5, Q6 supplies current to differential pairs Q1, Q2 and Q3, Q4. Current is supplied to the Q5, Q6 pair in turn by a current source I.sub.s1. When used in an ADC, Q5 is gated ON and Q6 OFF during a TRACK mode in which the V.sub.IN bias signal for Q1 tracks the varying input analog signal, while Q6 is gated ON and Q5 OFF during a LATCH mode to obtain a sample of the input analog signal value at the beginning of the LATCH mode. The alternation between TRACK and LATCH is governed by a clock circuit (not shown).
Assume that V.sub.IN is lower than V.sub.REF immediately prior to LATCH. More current will accordingly flow through Q2 than through Q1. Since the current through R.sub.L2 will also be higher than the current through R.sub.L1, R.sub.L2 will experience a greater voltage drop than R.sub.L1, setting V.sub.o LOW and V.sub.o HIGH. At the commencement of the LATCH cycle, the base of Q4 will thus be biased HIGH and the base of Q3 LOW. This turns Q4 on and Q3 off as Q6 is gated. The current through Q4 continues to generate a large voltage drop across R.sub.L2, keeping V.sub.o LOW. Conversely, the lack of current flow through Q3 results in a low or zero voltage drop across R.sub.L1, keeping V.sub.o HIGH. The circuit is thus latched at the logic output existing at the beginning of the sample period, until the commencement of the next TRACK cycle.
The speed of operation for the FIG. 1 circuit is not optimum. To make the transition from TRACK to LATCH, the Q1, Q2 pair must be discharged and turned off, the Q3, Q4 pair must be energized, and a further delay is required for the Q3, Q4 pair to regenerate to the final logic value. To go from LATCH to TRACK, the Q3, Q4 pair must be discharged from a hard saturation state and turned off, the Q1, Q2 pair must be charged and turned on, and a further delay is encountered while the currents through Q1 and Q2 settle before reverting to LATCH again. This limits the ADCs in which the latching comparators are used to lower frequency signal processing and communication systems. It would be very desirable to advance the ADCs into the high frequency portions of such systems where very high frequency signals must be digitized.